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DeFacTo is an innovative chip design software company developing breakthrough technology to dramatically enhance the DFT process and increase the testability of integrated circuits (ICs) and systems on a chip (SoCs).
DeFacTo’s vision is to enable designers to complete planning, analysis and insertion of integrated circuit test logic before synthesis by delivering a high quality suite of tools working at the register transfer level (RTL).
DeFacTo offers two products in order to accomplish this, HiDFT-SIGNOFF and HiDFT-STAR work seamlessly to analyze testability and perform RTL changes respectively.
HiDFT-SIGNOFF is a unique EDA tool that allows scan logic analysis at RTL. HiDFT-SIGNOFF permits designers to create a high-level design for test signoff methodology, closing the gap between RTL and DFT. HiDFT-SIGNOFF allows early identification of test issues and enables new pre-synthesis design and DFT verifications.
HiDFT-STAR (High level Design For Test – Structured Test ARchitectures) is a fully customizable RTL-to-RTL editing tool for IP cores and SOC blocks. HiDFT-STAR has shown to be effective in moving DFT implementation tasks from gate level to the RTL level. This silicon proven product has successfully helped the DFT engineer by moving the integration of memory BIST test logic from gate level to the RTL level. The main benefit is a significant reduction of TAT (Turn Around Time) which comes from the ease of this new RTL-to-RTL editing capability.
In The News
DATE 2011
![DateShow2011_thumb[1]](http://edatechforce.com/wp-content/uploads/2011/01/DateShow2011_thumb1.jpg "DateShow2011_thumb[1]")
Visit DeFacTo booth at the conference Design, Automation and Test in Europe 2011, in Grenoble
Press Release
11/1/2010 – Ricoh uses DeFacto’s DFT tool for complex designs
PARIS – Ricoh Company Ltd. said it has licensed the HiDFT-SIGNOFF Design-for-Test (DFT) solution from France-based EDA startup DeFacTo Technologies SA and reduced turnaround time during DFT process.
