HiDFT-SIGNOFF & HiDFT-STAR
How would you like to check your RTL design’s DFT quality, assess its testability using DFT Design Rule Checking and measure its test coverage all without going through the traditional synthesis process? RTL-DFT methodology lets you build a robust design by removing obstacles to test at the RTL (architectural) level. This can now be accomplished using HiDFT-SIGNOFF from DeFacTo Technologies.
DFT optimization can for the first time now be done at the RTL level with HiDFT-STAR, DeFacTo’s second product. HiDFT-STAR performs fully documented RTL-to-RTL edits negating the need for complicated and time consuming gate level ECOs.
DFT changes are built directly into your RTL for better portability and repeatability. Why solve the same problem again and again at the gate level? Apply your DFT methodology early and with confidence. Up until now DFT Engineers ran tests post-synthesis in two steps:
- DFT implementation
- ATPG process
Iterations at the gate level are costly and very common. For the first time ever, using HiDFT-SIGNOFF allows the DFT engineer to solve all DFT issues at the RTL stage before synthesis has even begun. HiDFT-SIGNOFF and HiDFT-STAR allow the design engineer to build a strong DFT platform from which they can have confidence in the DFT process at the RTL level.
In addition, integrating DFT at RTL allows quicker timing closure during gate level design. Another important advantage is that the verification engineer receives a test-ready RTL to simulate and verify, ensuring that nothing has been broken by the DFT engineer. Conversely, traditional verification at gate level is very slow and difficult to correct when problems introduced by DFT insertion occur.
