The following are highlighted features.
- Patented technologies for sequential, low power, and DFT synthesis
- Easy to adopt: compatible usage, Verilog/VHDL, SDC, Synopsys .lib / CCS
- Highly crafted architectures and implementations for data-path & logic operator components (e.g. adder, multiplier, and many others) for best constraint optimizations
- Low power synthesis: clock gating, operator isolation, leakage power optimization, power analysis
- DFT synthesis: scan cell replacement, DFT rule violation checking and fixing, scan chaining and stitching, DFT preview & reporting
- Largest amount of area and power reduction while meeting timing constraints
