F.A.Q.

FloorDirector is a Unix-based Electronic Design Automation (EDA) tool developed for the semiconductor design industry. It reduces on-chip dynamic peak currents and power noise generated by synchronous switching in the digital blocks, which is a fundamental problem in all types of IC designs today.

The semiconductor industry has been compensating for on-chip dynamic peak currents for many years with physical implementation techniques, e.g. using area hungry on-chip decoupling capacitors and expensive flip-chip packages. But this approach has – due to speed, size and complexity – arrived at a point where it is no longer sufficient in demanding designs.

Instead of this classical approach, FloorDirector focuses on removing the root cause of the problem. It analyzes the dynamic behavior of a design and provides directives for implementing the clock tree in a way that meets the original performance specifications, but with significantly reduced dynamic peak currents.

By addressing the fundamental problem from new angle, FloorDirector optimization results will co-exist with the traditional physical compensation approach.

FloorDirector uses a native Static Timing Analysis (STA) engine, to ensure that timing is not violated during optimization. As input to this, FloorDirector imports Standard Delay Format (SDF) files extracted from your original design. This approach prevents introducing a new delay extraction engine into your flow and guarantees 100% correlation in the delays themselves. During STA, which is known by customer experience to correlate perfectly with existing sign-off timing analysis tools, FloorDirector chooses a conservative view, never over-extending design timing.

As an integral part of the design optimization, timing consistency is checked concurrently with dynamic power and noise, thereby making sure timing remains intact.

Almost all designs have a certain percentage of timing-critical paths, that define the maximum performance of the chip. However, think of this as the ‘tip of the iceberg’; a small minority of paths cannot be touched, but the majority of paths – and hence the bulk of the power – will have available timing slack. It is a pattern we see over and over again; remaining slack will be small in some places or large in other places, but even in designs considered to have critical timing, FloorDirector is capable of creating a good solution for the design.

Both.

Vectorless is a straight forward approach to an immediate FloorDirector optimization. It emulates circuit activity in a general context, providing solutions that work well across all modes of operation.

While using VCD is uncomplicated, it obviously requires that you have a VCD available at the time of the optimization. However, if you are targeting a specific use-case, say, you want to reduce noise to improve Rx sensitivity in a wireless system, a VCD will explicitly describe that exact mode of operation, and the result will be better. Note, that you don’t have to select only one of them; FloorDirector supports concurrent optimization across multiple use-cases. So you can add as many combinations of VCD and vectorless as you like.

FloorDirector is broadly applicable. For several years, FloorDirector has been successfully proven on a variety of design, from very small designs (1,000 flip-flops) to large design blocks (400,000 flip-flops), ranging from 10 MHz to close to 1 GHz and implemented in processes of 0.35 µm down to 28 nm.

There are no specific factors which are prohibitive to achieving successful results. FloorDirector’s dynamic power noise optimization is considered useful across a wide range of designs in most semiconductor organizations.

Unclean timing is very common at the early stages of the design process. FloorDirector is designed to explicitly handle unclean timing. Designs may be optimized while accepting existing negative slack, but not worsening this. As such the violating paths, which may be known in the mind of the designer to be fixed later by other means in the backend flow, will remain untouched. Or even improved!

FloorDirector can be parametrized with a wealth of criteria for setup and hold timing margins, negative or positive slack, and in relation to either total accumulated slack or per-end-point.

To perform an optimization, FloorDirector needs commonly available library and design files, such as LEF, .lib, SDC, gate-level Verilog netlist, and SDF files. Additionally VCD, DEF and SPEF files can be used. While FloorDirector fully supports multi-mode-multi-corner operation, running in a single corner is a viable option too. In this case all data should be generated / extracted from the worst-case setup-time corner. During an evaluation, Teklatech will provide a document which fully describes the individual steps and file requirements.

The core functionality of FloorDirector is that of reducing the peak and softening the slope of the dynamic peak current.

We call this Dynamic Power Shaping™.

However, the most important feature – or, benefit if you wish – depends on what is the key to design success in your application; Power Integrity, Noise Integrity, both? Power integrity will be greatly improved from the FloorDirector optimizations, but so will on-chip substrate noise and EMI which are key parameters for designers of mixed-signal and RF products.

Actually, none!

FloorDirector is a non-intrusive tool. After an optimization, FloorDirector will generate a set of Clock Tree Synthesis (CTS) directives targeted for your specific CTS tool of choice. These directives are then merged with your existing CTS script, and used by the CTS tool during Clock Tree Synthesis. This means, that FloorDirector will not intrude in your design flow or modify your design database, but will simply enhance and strengthed the performance of your existing EDA flow.